Description: DA算法中的使用的查找表模块，本程序先设计查找表，然后设计4*4DA算法模块，之后进行位扩展和字扩展得到32阶滤波器程序.附带4各表，和FIR滤波器序数-DA algorithm used in the lookup table module, the design of the program first look-up table, and then design 4* 4DA algorithm module, after the word-bit expansion and extension of the procedure to be 32-order filter Platform: |
Size: 10240 |
Author:黄萌 |
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Description: VHDL编写的代码。采用流水线方法实现的FIR滤波器。22阶。Fa=48kHz, Fc=10KHz。可用ModeSim仿真并FPGA实现-Code written in VHDL. Line method using the FIR filter. 22 bands. Fa = 48kHz, Fc = 10KHz. Can be used to achieve ModeSim simulation and FPGA Platform: |
Size: 1024 |
Author:李乔 |
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Description: 可编程的FIR滤波器VHDL实现，只要输入FIR的阶数以及系数，就可在FPGA中实现FIR滤波器-Programmable FIR filter VHDL implementation, simply enter the order number as well as the FIR coefficients, we can implement FIR filters in FPGA Platform: |
Size: 3072 |
Author:wuyihua |
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Description: This code is a VHDL based code for FIR filter.A finite impulse response (FIR ) filter is a type of a digital filter. The impulse response, the filter s response to a Kronecker delta input, is finite because it settles to zero in a finite number of sample intervals. Platform: |
Size: 44032 |
Author:kumar |
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Description: This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the system.
The power consumption of various arithmetic architectures has been investigated, and the results have been provided in the intial report (FIRLowPowerConsiderations.doc). These results have enabled the correct power/performance optimization for the FIR filter design. Platform: |
Size: 447488 |
Author:Nagendran |
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Description: 本文运用vhdl语言，研究了对于FIR滤波器（流水线）的实现与改进，欢迎学习-In this paper, vhdl language study for the FIR filter (line) implementation and improvement are welcome to learn Platform: |
Size: 305152 |
Author:zhaobinnan |
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Description: 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial. Platform: |
Size: 1024 |
Author:许成 |
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Description: 在quartus ii 环境下，用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。
-In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter. Platform: |
Size: 1510400 |
Author:xuegamgma |
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Description: 在FPGA利用vhdl实现了32阶FIR滤波器。已经我利用了在几个对象。-In FPGA using VHDL to achieve a 32 order FIR filter. I ve used in many objects. Platform: |
Size: 12197888 |
Author:kc218 |
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Description: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers
etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm
(FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different
topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and
shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder,
carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective
is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative
study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on
the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis
of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is
used to implement the proposed designs in VHDL. Platform: |
Size: 1123027 |
Author:nalevihtkas |
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Search - fir filter in vhdl